1. Field of the Invention
The present invention relates to a semiconductor memory cell, and more particularly to a memory cell for a static random-access memory.
2. Description of the Prior Art
Conventional silicon LSI circuits include a static random-access memory (SRAM) composed of memory cells each comprising flip-flops coupled in a cross connection for storing data. Each of the memory cells has two storage nodes each including a region in which an impurity is diffused in a silicon substrate. The impurity-diffused region serves as the source or drain of a metal-insulator-silicon field effect transistor (MISFET). A MISFET whose source or drain is composed of a region where an impurity is diffused in a silicon substrate will hereinafter be referred to as an "intrasubstrate MISFET". The intrasubstrate MISFET has a gate electrode disposed over the silicon substrate with a silicon oxide film interposed therebetween, the silicon oxide film having a thickness in the range of from 10 nm to several tens nm.
Other than the intrasubstrate MISFET, there is also known a MISFET where a polycrystalline silicon film disposed over a substrate with one or more insulating films interposed therebetween is used as a source, a drain, and a channel. Such a MISFET is called a thin-film transistor (TFT). Recent years have seen many research and development efforts directed to TFTs.
While the TFT has its source, drain, and channel formed of a polycrystalline silicon film, a thin-film transistor whose channel substantially comprises a single crystal is called silicon-on-insulator (SOI) transistor, which has also been the subject of recent research and development attempts.
There has been reported an example in which P-channel TFTs are used as two load elements of flip-flops in a memory cell of an SRAM.
One example of an SRAM which has storage nodes in impurity-diffused regions in a substrate and uses P-channel TFTs as load elements is disclosed in Japanese Patent Laid-Open No. 202858/89 and Japanese Patent Laid-Open No. 166554/89.
One conventional SRAM memory cell will be described below with reference to FIGS. 1 through 5.
As shown in FIG. 1, the SRAM memory cell has an inverter I3 comprising a drive N-channel intrasubstrate MISFET Q5 and a load P-channel TFT P1, and an inverter I4 comprising a drive N-channel intrasubstrate MISFET Q6 and a load P-channel TFT P2. The inverter I3 includes a parasitic Schottky diode S1 connected between the drive N-channel intrasubstrate MISFET Q5 and the load P-channel TFT P1, and the inverter I4 includes a parasitic Schottky diode S2 connected between the drive N-channel intrasubstrate MISFET Q6 and the load P-channel TFT P2. These inverters I3, I4 have input and output terminals coupled in a cross connection for storing complementary potentials of "H" or "L" in two storage nodes N1, N2. When the stored information is not to be read from the memory cell or no information is to be written in the memory cell, the potential of a word line W is kept at a ground level to turn off two transfer N-channel intrasubstrate MISFETs Q7, Q8. To read the stored information from the memory cell or write some information in the memory cell, the potential of the word line W raised to a power supply potential level to turn on the MISFETs Q7, Q8 for reading or writing information through signal lines D1A, D2A.
FIG. 2 of the accompanying drawings is a plan view of all conductive layers of the memory cell shown in FIG. 1, and FIG. 3 of the accompanying drawings is a cross-sectional view taken along line III--III of FIG. 2. As shown in FIGS. 2 and 3, the memory cell includes a P-type silicon substrate 1, N-type impurity-diffused regions 2, conductive films 3 serving as the gate electrodes of N-channel intrasubstrate MISFETs, and conductive films 5 serving as the gate electrodes of P-channel TFTs. As shown in FIG. 5 of the accompanying drawings, a power supply potential interconnection 6Ab (Vcc), sources 6Ab, drains 6Ab, and channels 6Aa of the P-channel TFTs are composed of one polycrystalline silicon film. The signal lines D1A, D2A comprise aluminum interconnections 8. Connection holes C23, C25, C28, C36A interconnect the N-type impurity-diffused regions 2 and the conductive films 3, the N-type impurity-diffused regions 2 and the conductive films 5, the N-type impurity-diffused regions 2 and the aluminum interconnections 8, and the N-type impurity-diffused regions 2 and the drains 6Ab.
FIGS. 4 and 5 of the accompanying drawings show some of the conductive layers shown in FIG. 2. Specifically, FIG. 4 shows the N-type impurity-diffused regions 2 and the conductive films 3, whereas FIG. 5 shows the conductive films 5 and the power supply potential interconnection 6Ab, the drains 6Ab, and the channels 6Aa in the form of a polycrystalline silicon film. In FIG. 5, the polycrystalline silicon film includes regions 6Aa where no boron ions are injected and which serve as the channels of the P-channel TFTs, and regions 6Ab where boron ions are injected and which serve as the power supply potential interconnection, the sources and the drains of the P-channel TFTs.
Since the intrasubstrate MISFETs are employed in the flip-flops of the conventional SRAM memory cell, the storage nodes necessarily contain impurity-diffused regions in the substrate.
Uranium nuclides that are contained in a minute quantity in the package material of the LSI and the aluminum interconnection material produce alpha particles when they decay. When alpha particles pass through a substance, they cause ionization along the path of their travel.
If alpha particles pass through an impurity-diffused region when the storage node containing that impurity-diffused region is in an "H" state, then a potential change occurs in the impurity-diffused region and its surrounding region due to the ionization caused by the alpha particles. If electric charges collected by the potential change exceed a certain level, the storage node changes from the "H" state to an "L" state, thus destroying the information stored in the storage node. It is known that this phenomenon is primarily responsible for soft errors of the SRAM.
Such soft errors caused by alpha particles are unavoidable in those SRAMs which employ intrasubstrate MISFETs in flip-flops. Even though the quantity of uranium and thorium nuclides contained in LSI materials is greatly reduced at present because the purity of LSI materials is highly improved, soft errors are still causing serious problems with respect to the reliability of SRAMs in actual usage.
If flip-flops are constructed with TFTs or SOI transistors used as drive elements, then storage nodes may not contain impurity-diffused regions in a substrate. However, inasmuch as TFTs or SOI transistors do not have a sufficient current drive capability as compared with intrasubstrate MISFETs of the same size, if TFTs or SOI transistors are used in the conventional circuit arrangement, then the resultant memory cell is poor regarding the speed at which stored information is read from the memory cell.